UART framing and a SPI chip select

UART 8N1 idles high, drops for the start bit, then sends eight data bits least-significant first, then a stop bit that must be high. A stop bit that stays low is a framing error: the receiver was still in the byte when the line should have returned to idle.

SPI mode 0 clocks MOSI out most-significant first while chip select is held low. If CS rises before the eighth clock, the slave stops taking bits and the byte is cut in half. Read the UART byte and its stop bit, then the SPI byte and whether CS stayed down.